The present invention relates to a manufacturing method of a semiconductor device which is small in size and low in loss and which can be integrated, and a power conversion circuit.
With the object of electrically isolating elements in a semiconductor integrated circuit, a SOI (Silicon on Insulator) isolation structure having an insulation film provided on side faces and a bottom part of elements to be integrated is adopted. Especially in a semiconductor integrated circuit having a withstand voltage, element isolation becomes comparatively easy and consequently the SOI isolation structure is an effective structure.
A manufacturing method of a high withstand voltage semiconductor device using such SOI isolation is disclosed in, for example, an embodiment shown in FIG. 9 in JP-A-10-190000.
A semiconductor element disclosed in JP-A-10-190000 is manufactured by implanting boron (B) into a channel region on a Si substrate insulated by an oxide film and phosphorus (P) into a drift region on the Si substrate with an ion implanter, conducting thermal diffusion, and then forming a source layer and a drain layer. Furthermore, it is aimed at minimizing the area of a pn junction between the drift region and the channel region and improving the operation withstand voltage by adding an insulation structure between the channel region and the drain region.
According to a conventional art, a manufacturing method of changing and forming p-type and n-type ion implantation regions on a p-type Si substrate and forming, for example, a channel layer and a drift layer (drift region) of a MOSFET having a high withstand voltage is disclosed. In a high withstand voltage semiconductor device manufactured by using such a method, the withstand voltage of elements typically depends upon the activated impurity concentration of the drift layer, and varies with dispersion of the impurity concentration.
Especially in a high withstand voltage semiconductor using a SOI substrate, there are relations as shown in FIG. 7 between the withstand voltage and the impurity concentration of the drift layer. There is an optimum impurity concentration which maximizes the withstand voltage. Therefore, it is necessary to provide the withstand voltage with a margin with due regard to the dispersion of the impurity concentration.
As a result of study conducted by the present inventors, however, it has been found that the dispersion rate of the withstand voltage in a high concentration region is greater than the dispersion rate in a region where the concentration is lower than the optimum value and it is necessary to set the design center value of the impurity concentration in the drift layer lower than the optimum value in order to implement the withstand voltage more stably. As a result, the resistance of the drift layer increases and the resistance of the element increases, resulting in an increase of the element size.
Furthermore, since the withstand voltage also becomes lower at the same time, it is necessary to increase the element size in order to increase the withstand voltage.
In the case of the conventional art, the drift layer is formed by using the ion implantation method, and consequently the dispersion of the impurity concentration implanted into the drift layer is narrow, and the dispersion of the withstand voltage tends to be able to be narrowed. Since the withstand voltage is affected by an influence of the impurity concentration dispersion in a start substrate, however, the above-described problem occurs in the same way.
As for the drift layer formed by using the ion implantation method, it has been found by our study that the withstand voltage becomes higher as the spread of the impurity distribution becomes greater and the impurity distribution becomes closer to that at a constant concentration. Therefore, it has been found that there is also a problem that the withstand voltage becomes low with respect to a SOI substrate obtained by using a substrate with definite impurities previously introduced into bulk Si crystal at the time of manufacture intact as the drift layer and consequently reduction of the element size becomes difficult.
In addition, in a power converter using such a semiconductor device, the large-sized semiconductor element makes large-scale integration difficult and a resultant complex circuit causes a large size. Furthermore, a problem that the efficiency of the converter is lowered by an increased loss of elements is posed.
As described above, the conventional semiconductor device has a problem that the size becomes large because of the dispersion of the semiconductor wafer. Furthermore, the power converter using the conventional semiconductor device has a problem that it is difficult to reduce the size and the efficiency is lowered.